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WRL 89/5 Spritely NFS: Implementation and Performance of Cache-Consistency Protocols
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WRL 89/7 Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines
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WRL 89/8 A Unified Vector/Scalar Floating-Point Architecture
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WRL 89/9 Architectural and Organizational Tradeoffs in the Design of the MultiTitan CPU
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WRL 90/1 Noise Issues in the ECL Circuit Family
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WRL 90/2 Efficient Generation of Test Patterns Using Boolean Satisfiability
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WRL 90/3 Two Papers on Test Pattern Generation
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WRL 90/4 Virtual Memory vs. The File System
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WRL 90/5 Efficient Use of Workstations for Passive Monitoring of Local Area Networks
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WRL 90/6 A One-Dimensional Thermal Model for the VAX 9000 Multi Chip Units
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WRL 90/7 1990 DECWRL/Livermore Magic Release
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WRL 90/9 Pool Boiling Enhancement Techniques for Water at Low Pressure
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WRL 91/1 Writing Fast X Servers for Dumb Color Frame Buffers
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WRL 91/10 Experience with a Software-Defined Machine Architecture
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WRL 91/11 Network Locality at the Scale of Processes
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WRL 91/12 Cache Write Policies and Performance
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WRL 91/2 A Simulation-Based Study of TLB Performance
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WRL 91/3 Analysis of Power Supply Networks in VLSI Circuits
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WRL 91/4 TurboChannel T1 Adapter
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WRL 91/5 Procedure Merging with Instruction Caches
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